JTAG Boundary Scan Test Systems (IEEE 1149.1)

XJDemo Hardware

XJDemo is a fully populated demonstration board providing a kick-start to your understanding of XJTAG products.

The XJDemo board is provided free with XJTAG and comes complete with a tutorial demonstrating all the features of the XJTAG system.

The XJDemo board is supplied pre-assembled and fully tested and includes the following:

• Xilinx 9536XL CPLD
• Altera EPM3032 CPLD
• Array of 9 bi-colour LEDs
• Two input pushbuttons
• A two-position configuration switch
• 16K-bit static RAM
• 32K-bit serial EEPROM
• Debug links (simulate open and short circuits)
• XJLink connector
• A full XJTAG tutorial
• All XJEase source files
• Two sample application SVF files
• Circuit Diagram    (PDF, 85k)
• BSDL files and EDIF netlist

• XJEase
• XJAnalyser
• XJRunner
• XJLink
• XJIO Board
• XJAPI
• Product Documentation
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• What people are saying...

  "With tens of thousands of pins on each board, we recognized that it would not be possible to validate these circuits in a commercially realistic timescale without the use of a boundary scan test system.
  
  XJTAG powerful circuit visualization tool provides us with a simple graphical view of the state of all JTAG pins across the multiple BGA devices and enables us to quickly pinpoint specific faults on our boards and speed up the whole debug process."
  
  Spencer Saunders, Engineering Manager, Platforms, Development Systems, ARM
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